In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate charge or capacitance in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices.
The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, two or more layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer, with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.
However, a problem may occur during the final processing steps when a buried contact is required to make contact to the substrate between fabricated storage capacitors (particularly stacked capacitors that are fabricated by any process steps). If the masking alignment used to define the buried contact isn't precise when the contact opening is etched, a portion of the storage node plate may be severed. Once this happens, there is an exposed interface between the capacitor's cell plates that lends itself to future plate to plate leakage.
The present invention improves existing capacitor fabrication processes, and in particular stacked capacitor processes, by optimizing a capacitor cell with passivation oxidation techniques that improve cell leakage and maintain cell area.